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SI9110/9111
Vishay Siliconix
High-Voltage Switchmode Controllers
FEATURES
* * * * 10- to 120-V Input Range * Internal Start-Up Circuit Current-Mode Control * Internal Oscillator (1 MHz) High-Speed, Source-Sink Output Drive * SHUTDOWN and RESET High Efficiency Operation (> 80%) * Reference Selection SI9110 - 1% Si9111 - 10%
DESCRIPTION
The SI9110/9111 are BiC/DMOS integrated circuits designed for use as high-performance switchmode controllers. A highvoltage DMOS input allows the controller to work over a wide range of input voltages (10- to 120-VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce internal power consumption to less than 10 mW. A push-pull output driver provides high-speed switching for MOSPOWER devices large enough to supply 50 W of output power. When combined with an output MOSFET and transformer, the SI9110/9111 can be used to implement single-ended power converter topologies (i.e., flyback, forward, and cuk). The SI9110/9111 is available in 14-pin plastic DIP and SOIC packages, and are specified over the industrial, D suffix (-40 to 85C) temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
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S-60752--Rev. F, 05-Apr-99 1
SI9110/9111
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (Note: VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 V Logic Inputs (RESET, SHUTDOWN, OSC IN, OSC OUT) . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SENSE, BIAS, VREF) . . . . . . . . . . -0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . .5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b. . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 14-Pin SOIC (Y Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (JA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167C/W 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/C above 25C. c. Derate 7.2 mW/C above 25C.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 120 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 k to 1 M Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Reference
SI9110 Output Voltage VR OSC IN = - VIN (OSC Disabled) RL = 10 M Si9111 SI9110 Si9111 Output Impedance
e
D Suffix
-40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k
Tempb
Typc
Mind
Maxd
Units
Room Room Full Full Room
4.0 4.0
3.92 3.60 3.86 3.52
4.08 4.40 4.14 4.46 45 130 1.0 k A mV/C V
ZOUT ISREF TREF VREF = -VIN
30 100 0.50
15 70
Short Circuit Current Temperature Stabilitye
Room Full
Oscillator
Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente fMAX fOSC f/f TOSC ROSC = 0 ROSC = 330 k
f
Room Room Room Room Full
3 100 200 10 200
1 80 160 120 240 15 500
MHz kHz % ppm/C
ROSC = 150 k f f/f=f(13.5 V) - f(9.5 V)/ f(9.5 V)
S-60752--Rev. F, 05-Apr-99 2
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SI9110/9111
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Error Amplifier
Feedback Input Voltage Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gaine Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Power Supply Rejection VFB IFB VOS AVOL BW ZOUT IOUT PSRR Source (VFB = 3.4 V) Sink (VFB = 4.5 V) 9.5 V VCC 13.5 V OSC IN = - VIN (OSC Disabled) FB Tied to COMP OSC IN = - VIN (OSC Disabled) SI9110 Si9111 Room Room Room Room Room Room Room Room Room Room 4.00 4.00 25 15 80 1.3 1000 -2.0 0.15 70 0.12 50 60 1 2000 -1.4 3.96 3.60 4.04 4.40 500 40 V nA mV dB MHz mA dB
D Suffix
-40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k
Tempb
Typc
Mind
Maxd
Units
OSC IN = - VIN, VFB = 4 V
Current Limit
Threshold Voltage Delay to Outpute VSOURCE td VFB = 0 V VSENSE = 1.5 V, See Figure 1. IIN = 10 A VCC 9.4 V Pulse Width 300 s, VCC = VULVO IPRE-REGULATOR = 10 A Room Room 1.2 100 1.0 1.4 150 V ns
Pre-Regulator/Start-Up
Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG - VUVLO +VIN +IIN ISTART VREG VUVLO VDELTA Room Room Room Room Room Room 15 8.6 8.1 0.6 8 7.8 7.0 0.3 9.4 8.9 V 120 10 V A mA
Supply
Supply Current Bias Current ICC IBIAS CLOAD < 75 pF (Pin 4) Room Room 0.6 15 0.45 10 1.0 20 mA A
Logic
SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Width
e
tSD tSW tRW tLW V IL VIH IIH IIL
CL = 500 pF, VSENSE -VIN See Figure 2. See Figure 3.
Room Room Room
50 50 50 25
100
ns
Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low
See Figure 3.
Room Room Room
2.0 8 1 -25 -35 5
V
VIN = 10 V VIN = 0 V
Room Room
A
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S-60752--Rev. F, 05-Apr-99 3
SI9110/9111
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Output
Output High Voltage Output Low Voltage Output Resistance Rise Timee Fall Timee VOH VOL ROUT tr tf IOUT = -10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF Room Full Room Full Room Full Room Room 20 25 40 40 9.7 9.5 0.30 0.50 30 50 75 75
D Suffix
-40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k
Tempb
Typc
Mind
Maxd
Units
V
ns
Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = v 5 pF.
TIMING WAVEFORMS
FIGURE 1.
FIGURE 2.
FIGURE 3.
S-60752--Rev. F, 05-Apr-99 4
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SI9110/9111
Vishay Siliconix
TYPICAL CHARACTERISTICS
FIGURE 4.
FIGURE 5.
PIN CONFIGURATIONS
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SI9110/9111
Vishay Siliconix
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9110/ 9111 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN (pin 2) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC (pin 6). This startup circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 8.6 V. If VCC is not forced to exceed the 8.6-V threshold, then VCC will be regulated to a nominal value of 8.6 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the undervoltage lockout threshold (typically 8.1 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 8.6 V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48-V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at BiC/DMOS as a function of input voltage. BIAS To properly set the bias for the SI9110/9111, a 390-k resistor should be tied from BIAS (pin 1) to -VIN (pin 5). This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15A. Reference Section The reference section of the SI9110 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9110 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1% of 4 V. This compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Applications which use a separate external reference, such as non-isolated converter topologies and circuits employing optical coupling in the feedback loop, do not require a trimmed voltage reference with 1% accuracy. The Si9111 accommodates the requirements of these applications at a lower cost, by leaving the reference voltage untrimmed. The 10% accurate reference thus provided is sufficient to establish a dc bias point for the error amplifier. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization is accomplished by capacitive coupling of a positive SYNC pulse into the OSC IN (pin 8) terminal. For a 5-V pulse amplitude and 0.5-s pulse width, typical values would be 100 pF in series with 3 k to pin 8. SHUTDOWN and RESET SHUTDOWN (pin 11) and RESET (pin 12) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. TABLE 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN
H H L H
RESET
H
Output
Normal Operation Normal Operation (No Change) Off (Not Latched)
S-60752--Rev. F, 05-Apr-99 6
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